The evolution of the packaging technology has developed various types of semiconductor packages. For example, BGA (ball grid array) package employs advanced packaging technology to mount a semiconductor chip on a front side of a substrate and use the self-alignment technique to form an array of solder balls on a back side of the substrate. This allows a unit area on the substrate or chip carrier to accommodate more solder balls or input/output (I/O) connections to be suitable for the chip that is highly integrated, and the solder balls or I/O connections are used to bond and electrically connect the semiconductor package to an external device such as printed circuit board (PCB).
However, the above semiconductor package may cause significant problems during practical operation. Since there are a plurality of electronic elements and electronic circuits densely disposed on the chip, a huge amount of heat would be generated by these electronic elements and circuits; if the heat cannot be efficiently dissipated, the performance and lifetime of the chip may be damaged by overheat. Further, the semiconductor package lacks a shielding mechanism and thus is easily subject to external electromagnetic interference and noises.
In order to solve the above problems, a cavity-down BGA (CDBGA) package is provided as shown in FIG. 1, which is characterized in a cavity formed in a substrate to allow a semiconductor chip to be received in the cavity and attached to the substrate in a face-down manner. This CDBGA package 10 comprises a substrate 11, a heat sink 12, at least one semiconductor chip 13, a plurality of bonding wires 14, an encapsulation body 15, and a plurality of solder balls 16.
The substrate 11 has a front side 11a and a back side 11b and is formed with an cavity 111. The heat sink 12 is made of a good thermally conductive material such as copper and is attached to the front side 11a of the substrate 11 to seal one end opening of the cavity 111. The chip 13 has an active surface 13a and an inactive surface 13b. The chip 13 is received in the cavity 111 in a face-down manner that the inactive surface 13b is attached to the heat sink 12. A wire-bonding process is performed to form the plurality of bonding wires 14 that electrically connect the active surface 13a of the chip 13 to the substrate 11. Then a molding process is carried out to form the encapsulation body 15 that completely encapsulates the chip 13 and the bonding wires 14. Finally a ball-implanting process is performed to implant the plurality of solder balls 16 on the back side 11b of the substrate 11, such that the CDBGA package 10 is fabricated.
The heat sink in the above CDBGA package may desirably provide the heat-dissipating and shielding effects. However, the solder balls for connecting the package to the external PCB must be made with a height larger than a height of wire loops of the bonding wires protruding on the back side of the substrate; this arrangement restricts the routability on the substrate and set a limitation on the size of the solder balls. Moreover, the bonding wires bonded to the chip are densely arranged and easily subject to short circuit if adjacent bonding wires accidentally come into contact with each other, thereby making the wire-bonding process difficult to implement. During the molding process, the chip-bonded and wire-bonded substrate is placed in an encapsulation mold, an epoxy resin is injected into a cavity of the mold to form the encapsulation body encapsulating the chip and bonding wires that are received in the cavity. However in the practical operation, the substrate may not be tightly clamped by the mold due to the mismatch between clamping positions on the substrate and size of the cavity of the mold. When the epoxy resin is injected into the cavity, it would flash over unintended area on the substrate that is not tightly clamped; the resin flash degrades the appearance of the fabricated package and also adversely affects the quality of electrical connection of the package. Further, the injected resin is a fluid that generates mold flow impact on the bonding wires formed on the substrate. If the flow speed of the resin is unduly high, the mold flow impact would be great to shift the bonding wires and cause undesirable contact or short circuit between adjacent bonding wires, thereby severely damaging the quality and reliability of the fabricated package.
In addition, for general fabrication of semiconductor devices, chip carriers such as substrates or lead frames suitable for semiconductor devices are fabricated by a chip-carrier manufacturer. Then, these fabricated chip carriers are transferred to a packaging manufacturer and subject to chip-bonding, wire-bonding, molding and ball-implanting processes to form the semiconductor devices with desirable functionality that are requested by clients. Such fabrication processes involve different manufacturers, not only making the fabrication processes complex but also making the semiconductor devices difficult to change the design thereof.
Therefore, the problem to be solved herein is to provide a semiconductor device, which can be fabricated by simple processes and reduced cost and also can eliminate the above drawbacks of heat dissipation, electromagnetic interference and resin flash.